High Speed Level Converters With Short Circuit Current Reduction

Avireni Srinivasulu, Adipudi Bala Tripura Sundari

Abstract


The level converter is used as interface between low voltages to high voltage boundary. The efficient level converter has less power consumption and less delay are the design considerations of the level shifter. In this paper two new CMOS level converters are presented with high driving capability with low propagation delay. The proposed level converters are simulated using Cadence software with 0.18 µm CMOS technology. The simulation result shows that the proposed circuits have less propagation delay than the existing ones. The circuits are simulated for different load capacitor values and different voltages. The proposed level converters operate for different input pulse signal amplitudevalues are +0.8 V, +1 V, +1.2 V and VDDH values of +1.8 V and +3.3 V.


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References


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DOI: http://dx.doi.org/10.11601/ijates.v3i2.92

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